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北京益联亚迅科技有限公司

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北京益联亚迅科技有限公司位于有中国硅谷之称的“中关村”高新技术产业区,是一家在中国地区专门从事计算机行业的高科技公司。始创于2003年,已具有10多年的品牌历史,既致力于在中国分销世界一流的并基于企业级解决方案中最必须的计算机硬件及网络产品,并作为能够向合作伙伴及企业客户提供解决方案的技术服务商。北......

intel X520-SR2(E10G42BFSR)万兆双口多模服务器网卡

产品编号:5519673                    更新时间:2013-11-04
价格: ¥2950.00

北京益联亚迅科技有限公司

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产品详情

intel® Ethernet Server Adapter X520-SR2Intel® Ethernet X520 Server Adapters

Ultimate flexibility and scalability in virtual and unified storage environments

Intel’s new family of Intel® Ethernet X520 Server Adapters are the most flexible and scalable Ethernet adapters for today’s demanding data center environments.

The Intel® Ethernet X520 Server Adapter family addresses the demanding needs of the next-generation data center by providing unmatched features for virtualization, flexibility for LAN and SAN networking, and proven, reliable

Intel® 82599 10 Gigabit Ethernet Controller

Industry-leading, energy-efficient design for next-generation 10 Gigabit performance and multi-core processors

Low-profile

Enables higher bandwidth and throughput from standard and low-profile PCIe slots and servers

Load balancing on multiple CPUs

Increases performance on multi-processor systems by efficiently balancing network loads across
CPU cores when used with Receive-Side Scaling (RSS) from Microsoft or Scalable I/O on Linux*

iSCSI remote boot support

Provides centralized storage area network (SAN) management at a lower cost than other iSCSI soluti***

Support for most network operating systems (NOS)

Enables widespread deployment

RoHS-compliant2

Complies with the European Union directive 2002/95/EC to reduce the use of hazardous materials

Intel® PROSet utility for Microsoft Windows* Device Manager

Provides point-and-click management of individual adapters, advanced adapter features, connection
teaming, and virtual local area network (VLAN) configuration

Time Sync (IEEE 1588, 802.1as)

Lets networked Ethernet equipment synchronize internal clocks according to a network master clock;
endpoint can then acquire an accurate estimate of the master time by compensating for link latency

 

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