Key Features
*VDD = 1.8 +/- 0.1V
*VDDQ = 1.8 +/- 0.1V
*All inputs and outputs are compatible with SSTL_18 interface
*8 banks
*Fully differential clock inputs (CK, /CK) operation
*Double data rate interface
*Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS)
*Differential Data Strobe (DQS, DQS)
edges when read (edged DQ)
*Data outputs on DQS, DQS
*Data inputs on DQS centers when write(centered DQ)
transition with CK transition
*On chip DLL align DQ, DQS and DQS
*DM mask write data-in at the both rising and falling edges of the data strobe
*All addresses and control inputs except data, data strobes and data masks latched on the rising
edges of the clock
*Programmable CAS latency 3,4, 5, 6 and 7 supported
*Programmable additive latency 0, 1, 2, 3, 4 and 5 supported
*Programmable burst length 4/8 with both nibble sequential and interle***e mode
*Internal eight bank operati*** with single pulsed RAS
*Auto refresh and self refresh supported
*tRAS lockout supported
*8K refresh cycles /64ms
*JEDEC standard 84ball FBGA(x16)
*Full strength driver option controlled by EMR
*On Die Termination supported
*Off Chip Driver Impedance Adjustment supported
*Read Data Strobe supported (x8 only)
*Self-Refresh High Temperature Entry
****erage Refresh Period 7.8us at lower than Tcase 85C, 3.9us at 85C<Tcase<95C
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迪创科技有限公司 DigiTron Technology Limited
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